STM32未使用引脚的处理方式及推荐硬件设计规范

引用原文(AN2586)

All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources.

To increase EMC performance,unused clocks,counters or I/Os,should not be left free,e.g.I/Os should be set to “0” or “1”( pull-up or pull-down to the unused I/O pins.) and unusedfeatures should be “frozen” or disabled.

顺带将其他相关推荐设计摘录如下：
5.1 Printed circuit board
For technical reasons,it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (VSS) and another dedicated to the VDD supply. This provides good decoupling and a good shielding effect. For many applications,economical reasons prohibit the use of this type of board. In this case,the major requirement is to ensure a good structure for ground and for the power supply.

5.2 Component position
A preliminary layout of the PCB must separate the different circuits according to their EMI contribution in order to reduce cross-coupling on the PCB,that is noisy,high-current circuits,low-voltage circuits,and digital components.

5.3 Ground and power supply (VSS,VDD)
Every block (noisy,low-level sensitive,digital,etc.) should be grounded individually and all ground returns should be to a single point. Loops must be avoided or have a minimum area.The power supply should be implemented close to the ground line to minimize the area of the supply loop. This is due to the fact that the supply loop acts as an antenna,and is therefore the main transmitter and receiver of EMI. All component-free PCB areas must be filled with additional grounding to create a kind of shielding (especially when using singlelayer PCBs).

5.4 Decoupling
All pins need to be properly connected to the power supplies. These connections,including pads,tracks and vias should have as low an impedance as possible. This is typically achieved with thick track widths and,preferably,the use of dedicated power supply planes in multilayer PCBs. In addition,each power supply pair should be decoupled with filtering ceramic capacitors C (100 nF) and a chemical capacitor C of about 10 μF connected in parallel on the STM32F10xxx device. These capacitors need to be placed as close as possible to,or below,the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF,but exact values depend on the application needs. Figure 13 shows the typical layout of such a VDD/VSS pair.

Figure 13. Typical layout for VDD/VSS pair

5.5 Other signals When designing an application,the EMC performance can be improved by closely studying: ● sigNals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals,and not the case for LEDcommands).For these signals,a surrounding ground trace,shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve EMC performance.For digital signals,the best possible electrical margin must be reached for the two logical states and slow Schmitt triggers are recommended to eliminate parasitic states. ● Noisy signals (clock,etc.) ● Sensitive signals (high impedance,etc.)