问题描述
我想在SpinalHDL中将三元条件作为Verilog中的三元分配:
例如
wire my_condition = (this == that);
wire [1:0] my_ternary_wire = my_condition ? 2'b10 : 2'b01;
所需的SpinalHDL代码:
val myCondition = this === that
val myTernaryWire = myCondition ? B(3) : B(1)
解决方法
我刚刚看到可以使用:
val myCondition = this === that
val myTernaryWire = myCondition ? B(3) | B(1)
只需将:
更改为|