VHDL枚举器关系运算符

问题描述

我目前正在VHDL中对系统进行编程，并且正在使用另一个名为vnir的软件包中的枚举器，其定义如下：

package vnir is
    type row_type_t is (ROW_NONE,ROW_NIR,ROW_BLUE,ROW_RED);
end package vnir;

我已经这样定义了我的架构

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.vnir;

entity imaging_buffer is
    port(
        clock           : in std_logic;
        reset_n         : in std_logic;
        vnir_row_ready  : in vnir.row_type_t
    );
end entity imaging_buffer;

architecture rtl of imaging_buffer is
    signal vnir_row_ready_i : vnir.row_type_t;
begin
    vnir_pipeline : process (reset_n,clock) is
    begin
        if (reset_n = '0') then
            vnir_row_ready_i <= vnir.ROW_NONE;
        elsif rising_edge(clock) then
            if (vnir_row_ready /= vnir.ROW_NONE) then
                --do stuff
            end if;
       end if;
    end process vnir_pipeline;
end architecture;

内部信号vnir_row_ready_i可以毫无问题地分配，但是关系运算符似乎不起作用，因为当我尝试编译时，ModelSim会引发此错误：

# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): (vcom-1581) No feasible entries for infix operator '/='.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(23): Type error resolving infix expression "/=" as type std.STANDARD.BOOLEAN.
# ** Error: C:/Users/nashg/Documents/iris_project/ex2_iris/vhdl/subsystems/sdram/Imaging Buffer/test.vhd(28): VHDL Compiler exiting

解决方法

我的同事帮助我弄清楚了如何使其工作！我认为/ =运算符是在vnir范围内创建的，但未移植到我正在处理的实体上。通过在编译文件的开头写入：use work.vnir."/=";，使完整实体看起来像这样：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.vnir;
use work.vnir."/=";

entity imaging_buffer is
    port(
        clock           : in std_logic;
        reset_n         : in std_logic;
        vnir_row_ready  : in vnir.row_type_t
    );
end entity imaging_buffer;

architecture rtl of imaging_buffer is
    signal vnir_row_ready_i : vnir.row_type_t;
begin
    vnir_pipeline : process (reset_n,clock) is
    begin
        if (reset_n = '0') then
            vnir_row_ready_i <= vnir.ROW_NONE;
        elsif rising_edge(clock) then
            if (vnir_row_ready /= vnir.ROW_NONE) then
                --do stuff
            end if;
       end if;
    end process vnir_pipeline;
end architecture;

或者，它通过包含use work.vnir.all;并取出vnir来起作用。在类型之前，但这在我正在开发的项目中是不可能的

modelsim vhdl