Modelsim VHDL测试平台

编程问答 2022-08-11

问题描述

这是我在Modelsim中的VHDL代码。问题是输出未初始化，如您在图像中所见。请告诉我我的代码有什么问题。

library ieee;
use ieee.std_logic_1164.All;
use IEEE.NUMERIC_STD.ALL;
entity circu_it is 
port (A : in std_logic;
      B : in std_logic;
      C : in std_logic;
      D : in std_logic;
      Z : out std_logic );
end circu_it;
architecture Behavioral of circu_it
is
Signal E,F,M,N,L: std_logic;
begin
M <= (A and B and C) after 5ns;
E <= (M or D) after 5ns;
N <= (B nor C) after 5ns;
F <= (N nand A) after 5ns;
L <= not F after 2ns;
Z <= L xor E  after 5ns;
end Behavioral;

代码测试平台如下…… 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity delay_test is
end delay_test;
architecture stimulus of delay_test is
 component delay
 port (
      A : in std_logic;
      B : in std_logic;
      C : in std_logic;
      D : in std_logic;
      Z : out std_logic);
 end component;

 signal A: std_logic ;
 signal B: std_logic ;
 signal C: std_logic ;
 signal D: std_logic ;
 signal Z: std_logic ;
begin
 DUT: delay port map ( A => A,B => B,C => C,D => D,Z => Z);
 STIMULUS1: process
constant PERIOD: time := 100 ns;
 begin
 
 A <= '0';
 B <= '0';
 C <= '0';
 D <= '0';

wait for period;

 A <= '0';
 B <= '0';
 C <= '0';
 D <= '1';

wait for period;
 A <= '0';
 B <= '0';
 C <= '1';
 D <= '0';

wait for period;
 A <= '0';
 B <= '0';
 C <= '1';
 D <= '1';

wait for period;
 A <= '0';
 B <= '1';
 C <= '0';
 D <= '0';

 wait for period;
 A <= '0';
 B <= '1';
 C <= '0';
 D <= '1';

 wait for period;
 A <= '0';
 B <= '1';
 C <= '1';
 D <= '0';

wait for period;
 A <= '0';
 B <= '1';
 C <= '1';
 D <= '1';

wait for period;
A <= '1';
 B <= '0';
 C <= '0';
 D <= '0';

wait for period;
 A <= '1';
 B <= '0';
 C <= '0';
 D <= '1';

wait for period;
A <= '1';
 B <= '0';
 C <= '1';
 D <= '0';

wait for period;
A <= '1';
 B <= '0';
 C <= '1';
 D <= '1';

wait for period;
A <= '1';
 B <= '1';
 C <= '0';
 D <= '0';

wait for period;
A <= '1';
 B <= '1';
 C <= '0';
 D <= '1';

wait for period;
A <= '1';
 B <= '1';
 C <= '1';
 D <= '0';

wait for period;
A <= '1';
 B <= '1';
 C <= '1';
 D <= '1';
 wait;
 end process;
end stimulus;

解决方法

您的设计实体为circu_it。您已实例化名为delay的 component 。您要么需要

  • 编写一个配置以便将两个绑定在一起

  • 更改组件或实体的名称，以使它们相同（以便发生默认绑定）。

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