问题描述
我刚开始学习Verilog。我一直在尝试了解** Error (suppressible): /Documents/SystemVerilog2.sv(48): (vlog-2720) A generate begin/end pair has been found outside of generate construct.
** Error: (vlog-13069): /SystemVerilog2.sv(111): near "(": Syntax error,unexpected '('.
的操作顺序。我了解它的作用，但正在尝试确定范围。我认为下面的代码将是一个很好的例子，但是当我在Model Sim中编译它时，会出现以下错误。
module tutorial_led_blink
(
i_clock,i_enable,i_switch_1,i_switch_2,o_led_drive
);
input i_clock;
input i_enable;
input i_switch_1;
input i_switch_2;
output o_led_drive;
// Constants (parameters) to create the frequencies needed:
// Input clock is 25 kHz,chosen arbitrarily.
// Formula is: (25 kHz / 100 Hz * 50% duty cycle)
// So for 100 Hz: 25,000 / 100 * 0.5 = 125
parameter c_CNT_100HZ = 125;
parameter c_CNT_50HZ = 250;
parameter c_CNT_10HZ = 1250;
parameter c_CNT_1HZ = 12500;
// These signals will be the counters:
reg [31:0] r_CNT_100HZ = 0;
reg [31:0] r_CNT_50HZ = 0;
reg [31:0] r_CNT_10HZ = 0;
reg [31:0] r_CNT_1HZ = 0;
// These signals will toggle at the frequencies needed:
reg r_TOGGLE_100HZ = 1'b0;
reg r_TOGGLE_50HZ = 1'b0;
reg r_TOGGLE_10HZ = 1'b0;
reg r_TOGGLE_1HZ = 1'b0;
// One bit select
reg r_LED_SELECT;
wire w_LED_SELECT;
begin
// All always blocks toggle a specific signal at a different frequency.
// They all run continuously even if the switches are
// not selecting their particular output.
always @ (posedge i_clock)
begin
if (r_CNT_100HZ == c_CNT_100HZ-1) // -1,since counter starts at 0
begin
r_TOGGLE_100HZ <= !r_TOGGLE_100HZ;
r_CNT_100HZ <= 0;
end
else
r_CNT_100HZ <= r_CNT_100HZ + 1;
end
always @ (posedge i_clock)
begin
if (r_CNT_50HZ == c_CNT_50HZ-1) // -1,since counter starts at 0
begin
r_TOGGLE_50HZ <= !r_TOGGLE_50HZ;
r_CNT_50HZ <= 0;
end
else
r_CNT_50HZ <= r_CNT_50HZ + 1;
end
always @ (posedge i_clock)
begin
if (r_CNT_10HZ == c_CNT_10HZ-1) // -1,since counter starts at 0
begin
r_TOGGLE_10HZ <= !r_TOGGLE_10HZ;
r_CNT_10HZ <= 0;
end
else
r_CNT_10HZ <= r_CNT_10HZ + 1;
end
always @ (posedge i_clock)
begin
if (r_CNT_1HZ == c_CNT_1HZ-1) // -1,since counter starts at 0
begin
r_TOGGLE_1HZ <= !r_TOGGLE_1HZ;
r_CNT_1HZ <= 0;
end
else
r_CNT_1HZ <= r_CNT_1HZ + 1;
end
// Create a multiplexer based on switch inputs
always @ (*)
begin
case ({i_switch_1,i_switch_2}) // Concatenation Operator { }
2'b11 : r_LED_SELECT <= r_TOGGLE_1HZ;
2'b10 : r_LED_SELECT <= r_TOGGLE_10HZ;
2'b01 : r_LED_SELECT <= r_TOGGLE_50HZ;
2'b00 : r_LED_SELECT <= r_TOGGLE_100HZ;
endcase
end
assign o_led_drive = r_LED_SELECT & i_enable;
// Alternative way to design multiplexer (same as above):
// More compact,but harder to read,especially to those new to Verilog
// assign w_LED_SELECT = i_switch_1 ? (i_switch_2 ? r_TOGGLE_1HZ : r_TOGGLE_10HZ) :
(i_switch_2 ? r_TOGGLE_50HZ : r_TOGGLE_100HZ);
// assign o_led_drive = w_LED_SELECT & i_enable;
end
endmodule
# df is a pandas Dataframe
df_last_24 = df[df['Date']>=(dt.datetime.Now()-dt.timedelta(hours=24))]
ax = df_last_24.plot.line(x="Date",title="Air Qualty Index over the last 24 hours")
# Define the date format
years_fmt = mdates.DateFormatter('%I:%M %p')
ax.xaxis.set_major_formatter(years_fmt)
plot.axhline(linewidth=4,y=300,color='#731425',linestyle='-')
plot.text(0,300,'Hazardous',fontsize=10,va='center',ha='left',backgroundcolor='w')
plot.axhline(linewidth=4,y=200,color='#8c1a4b',200,'Very Unhealthy',y=150,color='#951d47',150,'Unhealthy',y=100,color='#e23127',100,'Unhealthy to Sensitive Groups',y=50,color='#f29d3a',50,'Moderate',backgroundcolor='w')
plot.show(block=True)
解决方法
摆脱第一个data: {data1: data1,data2: data2,data3: data3},//note comma not `;`
和最后一个begin。您的end块和always语句不需要用assign括起来。这就是“生成开始/结束”错误消息试图告诉您的内容。
请参阅IEEE Std 1800-2017，第27节。生成构造。