Vivado HLS对运行到无限循环中且带有警告“ Range is emptynull”和“ OPMODE 0110X0X with CARRYINSEL”的代码进行联合循环的仿真

编程问答 2022-06-11

问题描述

我正在尝试使用vivado_hls在硬件上实现简单的去马赛克算法。 c仿真和综合运行成功。当我运行RTL模拟时，起初它会警告我：

Starting static elaboration
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/mult_gen_v12_0/hdl/mult_gen_v12_0_vh_rfs.vhd:2255]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/mult_gen_v12_0/hdl/mult_gen_v12_0_vh_rfs.vhd:2240]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/floating_point_v7_1/hdl/floating_point_v7_1_vh_rfs.vhd:90362]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/floating_point_v7_1/hdl/floating_point_v7_1_vh_rfs.vhd:12604]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/floating_point_v7_1/hdl/floating_point_v7_1_vh_rfs.vhd:12604]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_rfs.vhd:375]
WARNING: [VRFC 10-1303] range is empty (null range) [/wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/ip/xilinx/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_vh_

我不明白警告range is empty的含义。

然后说完成了静态详细说明，然后继续编译软件包，体系结构和模块。之后，它进入vivado模拟器，并给我警告：

Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U1/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U2/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U3/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U4/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U5/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 165 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U6/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 175 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U15/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 175 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U16/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 175 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U17/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31065 ns  Iteration: 12  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U1/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31065 ns  Iteration: 12  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U2/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31225 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U15/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31225 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U16/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 011XX11 with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 31225 ns  Iteration: 16  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_deOg_U17/demosiac_filter_ap_dmul_3_max_dsp_64_u/U0/i_synth/mult/OP/R_AND_R/logic/R_AND_R/dsp48_e1/dsp48e1_add/DSP48E1_ADD/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 81675 ns  Iteration: 12  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U3/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 81715 ns  Iteration: 12  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U5/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.
Time: 81735 ns  Iteration: 11  Process: /apatb_demosiac_filter_top/AESL_inst_demosiac_filter/Loop_outer_loop_proc_U0/grp_demosiac_interpol_fu_160/demosiac_filter_fbkb_U3/demosiac_filter_ap_fadd_2_full_dsp_32_u/U0/i_synth/addsub_op/ADDSUB/speed_op/dsp/OP/dsp48e1_body/ALIGN_ADD/DSP2/DSP/prcs_opmode_drc  File: /opt/tools/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/primitive/DSP48E1.vhd
Warning: OPMODE Input Warning : The OPMODE 0110X0X with CARRYINSEL  000 to DSP48E1 instance is invalid.

而且持续进行了一个多小时。

我不确定这意味着什么，我尝试查找有关此错误的论坛，但在那儿找不到太多信息。

我在下面附了源代码

core(synthasizable part)

#include "demosiac_h.cpp"
#define min_def(x,y) ( (x)>(y) ? (y) : (x) )
#define max_def(x,y) ( (x)>(y) ? (x) : (y) )

pixel_8 demosiac_interpol(float win[3][3],int r,int c)
{
#pragma HLS PIPELINE II=1
#pragma HLS ARRAY_RESHAPE variable=win complete dim=1

    pixel_f new_pix; //i=col,j=rows
    pixel_8 new_pix_8;
    if (r % 2 == 0 && c % 2 == 0)
    {
        new_pix.r = (win[1][0] + win[1][2]) / 2;
        new_pix.g = win[1][1] * 2;
        new_pix.b = (win[0][1] + win[2][1]) / 2;
    }
    else if (r % 2 == 0 && c % 2 == 1)
    {
        new_pix.r = win[1][1];
        new_pix.g = (win[1][0] + win[2][1] + win[0][1] + win[1][2]) / 2;
        new_pix.b = (win[2][0] + win[0][2] + win[2][2] + win[0][0]) / 4;

    }
    else if (r % 2 == 1 && c % 2 == 0)//blue
    {
        new_pix.r = (win[0][2] + win[2][0] + win[2][2] + win[0][0]) / 4;
        new_pix.g = (win[1][0] + win[1][2] + win[2][1] + win[2][1]) / 2;
        new_pix.b = win[1][1];
    }
    else
    {
        new_pix.r = (win[0][1] + win[2][1]) / 2;
        new_pix.g = win[1][1] * 2;
        new_pix.b = (win[1][0] + win[1][2]) / 2;
    }
    new_pix_8.r =uc(max_def(min_def((new_pix.r*255.0),255.0),0.0));
    new_pix_8.g =uc(max_def(min_def((new_pix.g*255.0),0.0));
    new_pix_8.b =uc(max_def(min_def((new_pix.b*255.0),0.0));

    return new_pix_8;

}
void demosiac_filter(Stream_t& in,Stream_t& out)
{
#pragma HLS INTERFACE axis port=in
#pragma HLS INTERFACE axis port=out
//#pragma HLS INTERFACE s_axilite port=return   bundle=CONTROL_BUS

    //#pragma HLS INTERFACE s_axilite port=rows     bundle=CONTROL_BUS //offset=0x14
    //#pragma HLS INTERFACE s_axilite port=cols     bundle=CONTROL_BUS //offset=0x1C
    //#pragma HLS INTERFACE ap_stable port=rows
    //#pragma HLS INTERFACE ap_stable port=cols
#pragma HLS dataflow
//#pragma HLS inline
    uc pin,pout;
    float input_pix;
    float window[3][3];

    float line_buf[2][514];
#pragma HLS ARRAY_PARTITION variable=line_buf complete dim=1
    pixel_8 out_pix;
    outer_loop:for(int row=0; row<258;row++)
//#pragma HLS PIPELINE II=1
        {
        inner_loop:for(int col=0; col<514;col++)
            {
#pragma HLS PIPELINE II=1
                in >> pin;
                input_pix = ((float)pin)/256.0;
                window_loop:for (int i = 0; i < 3; i++)
                {
#pragma HLS UNROLL
                    window[i][0] = window[i][1];
                    window[i][1] = window[i][2];
                }
                window[0][2] = line_buf[0][col];
                window[1][2] = line_buf[0][col] = line_buf[1][col];
                window[2][2] = line_buf[1][col] = input_pix;

                if (row > 1 && col > 1 && row < 258  && col < 514 )
                {
                    out_pix = demosiac_interpol(window,row - 2,col - 2);
                    out<<out_pix.r;
                    out<<out_pix.g;
                    out<<out_pix.b;
                }

            }
        }

}

测试台：

Stream_t in("in_tb"),out("out_tb");
    for(int i=0; i<258;i++)
    {
        for(int j=0; j<514;j++)
        {
            in<<input[i][j];

        }
    }
    demosiac_filter(in,out);
    for(int i=0; i<256;i++)
        {
            for(int j=0; j<512;j++)
            {
                for(int k=0; k<3 ; k++)
                {
                    final_img[i][j][k]= out.read();
                }
            }
        }

标题（demosiac_h.cpp）：

//#include "ap_fixed.h"
#include "hls_stream.h"
typedef unsigned char uc;
typedef hls::stream<uc> Stream_t;
void demosiac_filter(Stream_t& in,Stream_t& out);
struct pixel_f
{
    float r;
    float g;
    float b;
};

struct pixel_8
{
    uc r;
    uc g;
    uc b;
};

我在这个问题上停留了将近一个星期。无法查明到底是什么问题！！ 由于不允许我附上完整的报告， 我已经在这里上传了 https://docs.google.com/document/d/1V0V9l20scS0IzHjp931Za7PMZWx_uQd-rYuz2xMlLq8/edit?usp=sharing

在调试此问题方面的任何帮助/建议将不胜感激

预先感谢

解决方法

暂无找到可以解决该程序问题的有效方法，小编努力寻找整理中！

如果你已经找到好的解决方法，欢迎将解决方案带上本链接一起发送给小编。

小编邮箱:dio#foxmail.com (将#修改为@）

c++image-processingvivadovivado-hls

相关问答

matplotlib报错：AttributeError: module 'backend_interagg' has no attribute 'FigureCanvas'. Did you mean: 'FigureCanvasAgg'?
使用本地python环境可以成功执行 import pandas as pd impor...
gitlab登录失败，报错：This challenge page was accidentally cached by an intermediary and is no longer available.
设置时间 控制面板
后端开发常见错误
错误1：Request method ‘DELETE‘ not supported 错误还原：...
docker常见错误
错误1：启动docker镜像时报错：Error response from daemon:...
idea常见错误
错误1：private field ‘xxx‘ is never assigned 按Alt...
pip安装依赖失败
报错如下，通过源不能下载，最后警告pip需升级版本 Requirem...