问题描述
我试图在Verilog中构建一个8位乘法器，但是当我去模拟模块的测试台时，我一直遇到这个奇怪的错误。它说：
Too many port connections. Expected 8,found 9
从模块和测试台如何列出9个变量来看，这实际上没有任何意义。任何帮助将不胜感激！
乘数模块
module my8bitmultiplier (output [15:0] O,output Done,Cout,input [7:0] A,B,input Load,Clk,Reset,Cin);
reg Done;
reg [1:0] state;
reg [7:0] A_reg,B_reg;
reg [15:0] A_temp,B_temp,O_temp,O_reg;
my16bitadder Adding(O_temp,A_temp,Cin);
always@(posedge Clk)
begin
if(Reset) assign state = {2'b00};
case(state)
0:
if(Load)
begin
A_reg = A;
B_reg = B;
O_reg = A_reg;
state = 1;
end
1:
begin
A_temp = A_reg;
B_temp = O_reg;
B_reg = B_reg - 1;
state = 2;
end
2:
begin
O_reg = O_temp;
if(B_temp)
begin
state = 1;
end
else
begin
state = 3;
Done = 1'b1;
end
end
3:
begin
Done = 1'b0;
state = 0;
end
endcase
end
endmodule
测试平台
module my8bitmultiplier_tb;
reg Load,Cin;
reg [7:0] A,B;
wire [15:0] O;
wire Done,Cout;
my8bitmultiplier dut(O,Done,A,Load,Cin);
always #5 Clk = ~Clk;
initial
begin
A = 8'b10;
B = 8'b10;
Load = 1;
Cin = 0;
#10 Load = 0;
#3000 A = 8'd100;
#3000 B = 8'd100;
#3000 Load = 1;
#3010 Load = 0;
#6000 A = 8'd150;
#6000 B = 8'd150;
#6000 Load = 1;
#6000 Load = 0;
begin
$display ($time,"A= %d B= %d O=%d ",O);
end
#10000 $finish;
end
endmodule
解决方法
当我在另一个模拟器上运行代码时，会收到一条更有用的警告消息：
reg Done;
|
xmvlog: *W,ILLPDX : Multiple declarations for a port not allowed in module with ANSI list of port declarations (port 'Done') [12.3.4(IEEE-2001)].
当我删除此行时，警告消失：
reg Done;
并更改：
module my8bitmultiplier (output [15:0] O,output Done,Cout,input [7:0] A,B,input Load,Clk,Reset,Cin);
收件人：
module my8bitmultiplier (output [15:0] O,output reg Done,Cin);
也许可以解决您在modelim上的问题。您也可以在edaplayground的不同模拟器上尝试代码。有时您会收到更多有用的消息。