问题描述
比方说,我有两个模块M1和M2,它们两个都输出32位数据。我想对每一位进行逻辑与。怎么做? 我一直在研究GitHub上的Library,但找不到用于AND操作的模块。
我接下来要做:
X[0] = M1[0] && M2[0]
X[1] = M1[1] && M2[1]
etc.
解决方法
add_gate的代码示例:
@gear
async def and_gate(arg1,arg2) -> (Uint[32]):
async with arg1 as a1:
async with arg2 as a2:
res = a1 & a2
yield res
@alternative(and_gate)
@gear
async def and_gate_one_arg(args) -> (Uint[32]):
async with args as (a1,a2):
res = a1 & a2
yield res
res_two = []
res_one = []
@gear
def consumer():
arg1 = once(val=31,tout=Uint[32])
arg2 = once(val=15,tout=Uint[32])
args = once(val=(15,31),tout=Tuple[Uint[32],Uint[32]])
bits_and_two_args = and_gate(arg1,arg2)
bits_and_one_arg = and_gate(args)
collect(bits_and_two_args,result=res_two)
collect(bits_and_one_arg,result=res_one)
consumer()
sim()
print(res_one)
print(res_two)