问题描述
首先，我是VHDL的新手，我试图创建RAM模型（或类似的东西）。该模型运行良好，我开始构建测试台，但是它没有重现从原始模型生成的信号文件的行为。主要问题是高阻抗信号“ ** Z ”变成“ U ”（未定义），并且在复位信号之后，值（ X“ 0000” * ）变成“ * X”。**“（未知）。我在测试台中有3个主要测试，以标签Test_N标记，但是第一个测试由于最后一个错误而失败了。因此，带有Test_1和Test_3的行被注释。这是RAM.vhd和RAM_TB.vhd的代码，其中有两个测试它们的屏幕截图。
RAM.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM is
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end RAM;
architecture BEH of RAM is
type MEM2KX16 is array(0 to 2047) of std_logic_vector(AD'range);
constant RAM_init : MEM2KX16 := (X"0000",others=>X"0000"); -- initial memory state
signal do : std_logic_vector(AD'range); -- signal for data output
signal addr : std_logic_vector(10 downto 0); -- 2047 = 0111 1111 1111,11 bits needed
signal addri : natural;
signal RAM_out : MEM2KX16; -- For debug purposes
begin
RG_ADDR : process (CLK,R)
begin
if (R = '1') then
addr <= "00000000000"; -- Reset address
elsif rising_edge(CLK) and AE = '1' then
addr <= AD(10 downto 0); -- Receive address
end if;
end process;
RAM2K : process (CLK,addr,addri)
variable RAM : MEM2KX16 := RAM_init;
begin
addri <= to_integer(unsigned(addr(10 downto 0)));
if rising_edge(CLK) then
if (WR = '1') then -- Write to memory
RAM(addri) := AD(15 downto 0);
end if;
if (R = '1') then -- Reset memory
do <= X"0000";
else
do <= RAM(addri); -- Return data from memory
end if;
end if;
RAM_out <= RAM; -- For debug purposes
end process;
TRI : AD <= do when (OE = '1') -- Three-state buffer
else "ZZZZZZZZZZZZZZZZ";
end architecture;
RAM_TB.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM_TB is
end entity;
architecture RAM_TB_arch of RAM_TB is
component RAM
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end component;
constant T : time := 20 ns;
signal CLK_TB,R_TB,WR_TB,AE_TB,OE_TB : std_logic;
signal AD_TB : std_logic_vector(15 downto 0);
begin
DUT : RAM port map (CLK_TB,OE_TB,AD_TB);
process
begin
CLK_TB <= '0';
wait for T/2;
CLK_TB <= '1';
wait for T/2;
end process;
STIMULUS : process
variable value : std_logic_vector(AD_TB'range) := X"FFFF";
variable addr : std_logic_vector(AD_TB'range) := X"0004";
begin
-- Test ZZZZ output of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '0'; -- No address
OE_TB <= '0'; -- No output
wait for 2*T;
--Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
-- Test input of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '1'; -- Read address
OE_TB <= '0'; -- No output
AD_TB <= addr; -- Address RAM(4)
wait for T;
WR_TB <= '1'; -- Write
AE_TB <= '0'; -- Do not read address
AD_TB <= value; -- Data to write
wait for T;
-- Test output of AD
WR_TB <= '0'; -- No write
OE_TB <= '1'; -- Output data from RAM
wait for T;
Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
-- Test Reset
R_TB <= '1'; -- Reset
wait for T;
--Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
wait;
end process;
end architecture;
RAM波形
RAM测试台波形
测试平台有什么问题？非常感谢您的帮助！
更新1
我在评论中遵循了Brian的建议，从而部分解决了问题。现在，第一个测试中的未初始化状态变为预期的高阻抗状态。但是状态“ X”仍然代替零。
RAM_TB.vhd中的更新代码
signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');
RAM_TB波形（更新1）
更新2
在RAM_TB.vhd中为Test_3更新了代码
R_TB <= '1'; -- Reset
AD_TB <= "ZZZZZZZZZZZZZZZZ";
wait for T;
RAM_TB波形（更新2）
解决方法
在@BrianDrummond和@Tricky的评论的指导下，我可以发布问题的答案。问题的原因及其解决方案可以在问题下方的注释中找到。
RAM_TB.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM_TB is
end entity;
architecture RAM_TB_arch of RAM_TB is
component RAM
port (CLK : in std_logic; -- Clock
R : in std_logic; -- Reset
WR : in std_logic; -- Write
AE : in std_logic; -- Address saving in temp.
OE : in std_logic; -- Signal about output word
AD : inout std_logic_vector(15 downto 0)); -- out address(11 bits address)/ in data(16 bits data)
end component;
constant T : time := 20 ns;
signal CLK_TB,R_TB,WR_TB,AE_TB,OE_TB : std_logic;
signal AD_TB : std_logic_vector(15 downto 0) := (others => 'Z');
begin
DUT : RAM port map (CLK_TB,OE_TB,AD_TB);
process
begin
CLK_TB <= '0';
wait for T/2;
CLK_TB <= '1';
wait for T/2;
end process;
STIMULUS : process
variable value : std_logic_vector(AD_TB'range) := X"FFFF";
variable addr : std_logic_vector(AD_TB'range) := X"0004";
begin
-- Test ZZZZ output of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '0'; -- No address
OE_TB <= '0'; -- No output
wait for 2*T;
Test_1 : assert AD_TB = "ZZZZZZZZZZZZZZZZ" report "[INFO] AD initial state is not ..Z..!" severity FAILURE;
-- Test input of AD
R_TB <= '0'; -- No reset
WR_TB <= '0'; -- No write
AE_TB <= '1'; -- Read address
OE_TB <= '0'; -- No output
AD_TB <= addr; -- Address RAM(4)
wait for T;
WR_TB <= '1'; -- Write
AE_TB <= '0'; -- Do not read address
AD_TB <= value; -- Data to write
wait for T;
-- Test output of AD
AD_TB <= "ZZZZZZZZZZZZZZZZ";
WR_TB <= '0'; -- No write
OE_TB <= '1'; -- Output data from RAM
wait for T;
Test_2 : assert AD_TB = value report "[INFO] AD output not equals value in RAM(addr)!" severity FAILURE;
-- Test Reset
wait for T;
R_TB <= '1'; -- Reset
AD_TB <= "ZZZZZZZZZZZZZZZZ";
wait for T;
Test_3 : assert AD_TB = X"0000" report "[INFO] AD output not equals zero after Reset!" severity FAILURE;
wait;
end process;
end architecture;