如何在XILINX FPGAArtix-7上实现HDMI直通

问题描述

我想在配备Artix-7 FPGA和HDMI宿/源端口的Nexys-Video板上实现自己的HDMI直通。我的设置是：PC HDMI端口连接到接收端口，而LED监视器连接到源HDMI端口。

由于板上没有TDMS编码器/解码器，因此我接下来还需要实现它们（我不想只抓住互联网上现成的一种封闭源实现）。但是现在，我只需要通过FPGA连接接收/源端口，这样我就可以在监视器上显示视频。但是，我还没有成功。没有图像显示，并且监视器显示“无信号”。我有点担心误用FGPA端口会导致电路板永久损坏。因此，我没有尝试所有事情。我希望得到一些建议来更正/完成我的代码。

我按照以下代码和原理图连接了HDMI信号：

module HDMI_Top(RSTN,CLK,BTN,SW,LED,HDMIR_TXEN,HDMIR_HPA,HDMIT_HPD,HDMIR_SCL,HDMIR_SDA,HDMIT_SCL,HDMIT_SDA,HDMIR_CLK_P,HDMIR_CLK_N,HDMIR_DATA_P,HDMIR_DATA_N,HDMIT_CLK_P,HDMIT_CLK_N,HDMIT_DATA_P,HDMIT_DATA_N);

input RSTN;
input CLK;
input [4:0] BTN;
input [7:0] SW;
output [7:0] LED;

output HDMIR_TXEN;
output HDMIR_HPA;
input HDMIT_HPD;
inout HDMIR_SCL;
inout HDMIR_SDA;
inout HDMIT_SCL;
inout HDMIT_SDA;

input HDMIR_CLK_P;
input HDMIR_CLK_N;
input [2:0] HDMIR_DATA_P;
input [2:0] HDMIR_DATA_N;
output HDMIT_CLK_P;
output HDMIT_CLK_N;
output [2:0] HDMIT_DATA_P;
output [2:0] HDMIT_DATA_N;

wire [2:0] HDMI_DATA;
wire HDMI_CLK;
wire w0,w1,w2;

assign LED = SW;
//assign HDMIR_HPA = HDMIT_HPD;
assign HDMIR_TXEN = 1'b1;
assign HDMIT_SCL = HDMIR_SCL;
assign HDMIT_SDA = HDMIR_SDA;

// IBUFDS: Differential Input Buffer
IBUFDS #(
    .DIFF_TERM("FALSE"),// Differential Termination
    .IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_hdmir_clk (
    .O(HDMI_CLK),// Buffer output
    .I(HDMIR_CLK_P),// Diff_p buffer input (connect directly to top-level port)
    .IB(HDMIR_CLK_N) // Diff_n buffer input (connect directly to top-level port)
);

OBUFDS #(
    .IOSTANDARD("DEFAULT") // Specify the output I/O standard
) OBUFDS_hdmit_clk (
    .O(HDMIT_CLK_P),// Diff_p output (connect directly to top-level port)
    .OB(HDMIT_CLK_N),// Diff_n output (connect directly to top-level port)
    .I(HDMI_CLK) // Buffer input
);

// IBUFDS: Differential Input Buffer
IBUFDS #(
    .DIFF_TERM("FALSE"),// Differential Termination
    .IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_hdmir_data [2:0] (
    .O(HDMI_DATA),// Buffer output
    .I(HDMIR_DATA_P),// Diff_p buffer input (connect directly to top-level port)
    .IB(HDMIR_DATA_N) // Diff_n buffer input (connect directly to top-level port)
);

OBUFDS #(
    .IOSTANDARD("DEFAULT") // Specify the output I/O standard
) OBUFDS_hdmit_data [2:0] (
    .O(HDMIT_DATA_P),// Diff_p output (connect directly to top-level port)
    .OB(HDMIT_DATA_N),// Diff_n output (connect directly to top-level port)
    .I(HDMI_DATA) // Buffer input
);endmodule

Here是与代码相对应的示意图。

谢谢；

解决方法

我终于开始工作了。现在，我的Nexys视频卡会通过全高清视频。详细信息如下：

HPA和TXEN引脚都必须设置为'1'。在我的情况下，我将源端口的HPD引脚分配给宿端口的HPA引脚。检查电路板原理图，将HPD引脚连接至开漏MOSFET，因此在分配之前必须将其反相。

分配HDMIR_HPA =〜HDMIT_HPD;

另外，在经过全面的搜索之后，我发现将接收端口的DDC SCL和SDA引脚桥接到源端口似乎是不可能的，因为无法（简单地）在FPGA上连接两个双向引脚。因此，解决该问题的方法是在接收器端添加EDID ROM仿真器。然后，FPGA本身就充当视频源设备（即我设置的PC）的监视器。

我从here找到了EDID ROM的VHDL实现。它模拟了1024 x 768显示器，但是我将其更改为1920 x 1080。

这是顶部模块的修订代码：

module HDMI_Top(
input RSTN,input CLK,input [4:0] BTN,input [7:0] SW,output [7:0] LED,output HDMIR_TXEN,output HDMIR_HPA,input HDMIT_HPD,input HDMIR_SCL,inout HDMIR_SDA,output HDMIT_SCL,inout HDMIT_SDA,input HDMIR_CLK_P,input HDMIR_CLK_N,input [2:0] HDMIR_DATA_P,input [2:0] HDMIR_DATA_N,output HDMIT_CLK_P,output HDMIT_CLK_N,output [2:0] HDMIT_DATA_P,output [2:0] HDMIT_DATA_N
);

wire HDMI_CLK;
wire [2:0] HDMI_DATA;

assign LED = SW;

// Whenever a sink is ready and wishes to announce its presence,it connects the 5V0 supply pin to the HPD pin. On
// the Nexys Video,this is done by driving the HPA (Hot Plug Assert) signal high. Note: this should only be done
// after a DDC channel slave has been implemented in the FPGA and is ready to transmit display data.
// FPGA lets the HDMI source (e.g.,a PC) connected to its sink port know its presence by setting HPA signal to '1'.
// A monitor connected to the source port sets HPD signal to '0'.
// assign HDMIR_HPA = 1'b1;
assign HDMIR_HPA = ~HDMIT_HPD;

// A pull-down resistor on the TXEN signal makes sure the sink buffer's transmitter facing the FPGA is disabled by default.
// An FPGA design using the sink port needs to actively drive this pin high for the buffer to pass data through.
assign HDMIR_TXEN = 1'b1;

// The Display Data Channel,or DDC,is a collection of protocols that enable communication between the display
// (sink) and graphics adapter (source). The DDC2B variant is based on I2C,the bus master being the source and the
// bus slave the sink. When a source detects high level on the HPD pin,it queries the sink over the DDC bus for video
// capabilities. It determines whether the sink is DVI or HDMI-capable and what resolutions are supported. Only
// afterwards will video transmission begin. Refer to VESA E-DDC specifications for more information.
edid_rom edid_rom_rx0 (.clk(CLK),.sclk_raw(HDMIR_SCL),.sdat_raw(HDMIR_SDA));
    
// IBUFDS: Differential Input Buffer
IBUFDS #(
    .DIFF_TERM("FALSE"),// Differential Termination
    .IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_hdmir_clk (
    .O(HDMI_CLK),// Buffer output
    .I(HDMIR_CLK_P),// Diff_p buffer input (connect directly to top-level port)
    .IB(HDMIR_CLK_N) // Diff_n buffer input (connect directly to top-level port)
);

OBUFDS #(
    .IOSTANDARD("DEFAULT") // Specify the output I/O standard
) OBUFDS_hdmit_clk (
    .O(HDMIT_CLK_P),// Diff_p output (connect directly to top-level port)
    .OB(HDMIT_CLK_N),// Diff_n output (connect directly to top-level port)
    .I(HDMI_CLK) // Buffer input
);

// IBUFDS: Differential Input Buffer
IBUFDS #(
    .DIFF_TERM("FALSE"),// Differential Termination
    .IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFDS_hdmir_data [2:0] (
    .O(HDMI_DATA),// Buffer output
    .I(HDMIR_DATA_P),// Diff_p buffer input (connect directly to top-level port)
    .IB(HDMIR_DATA_N) // Diff_n buffer input (connect directly to top-level port)
);

OBUFDS #(
    .IOSTANDARD("DEFAULT") // Specify the output I/O standard
) OBUFDS_hdmit_data [2:0] (
    .O(HDMIT_DATA_P),// Diff_p output (connect directly to top-level port)
    .OB(HDMIT_DATA_N),// Diff_n output (connect directly to top-level port)
    .I(HDMI_DATA) // Buffer input
); endmodule

您可以找到完整的源代码here。

我的下一步是向项目添加序列化器/解串器和tmds编码器/解码器。对于那些可能希望做同样事情的人，here是我（正在工作的）源代码的最新版本，包括序列化器/解串器和tmds编码器/解码器。

hdmi pass-through verilog xilinx

如何在XILINX FPGAArtix-7上实现HDMI直通

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