编译简单解码器时类型错误解析中缀表达式

问题描述

这是vhdl中的代码：

library IEEE;
use IEEE.std_logic_1164.all;
entity DECODER_TWO is
port
(
SW : in std_logic_vector(2 downto 1);
LD : out std_logic_vector(4 downto 1)
);
end DECODER_TWO;

architecture MY_FIRST_DECODER of DECODER_TWO is
begin
with SW select
 LD <= "1110" when "00",LD <= "1101" when "01",LD <= "1011" when "10",LD <= "0111" when "11",LD <= "1111" when others;
end MY_FIRST_DECODER;

当我尝试编译这个非常简单的 2 到 4 位解码器时，无论我做什么，都会收到错误消息

# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(15): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(16): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(17): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(18): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
# ** Error: C:/skole/in3160/oblig2/DecoderArchitect.vhd(19): VHDL Compiler exiting

我无法看到或理解问题是什么，因为我在第一行中没有收到 '

解决方法

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