GHDL：在库 WORK 中找不到实体

问题描述

当我尝试分析测试平台文件时出现此错误 (ghdl -a descodificador_tb.vhdl)：

descodificador_tb.vhdl:18:42：在图书馆“工作”

我正在单独学习 VHDL，并尝试创建测试平台文件，就像我在示例中看到的那样。代码如下：

library ieee;
use ieee.std_logic_1164.all;

entity descd_tb is 
end descd_tb;

architecture behave of descd_tb is
    component descd 
        port
        (
            E,A,B: in bit;
            D0,D1,D2,D3: out bit
        );
    end component;
    
    for descod: descd use entity work.descd;
    signal E,B,D0,D3: bit;
    
begin
    descod: descd port map (E => E,A => A,B => B,D0 => D0,D1 => D1,D2 => D2,D3 => D3);
    
    process
        type pattern_type is record
        --INPUT
        E,B: bit;
        --OUTPUT
        D0,D3: bit;
        end record;
        
        type pattern_array is array (natural range <>) of pattern_type;
        constant patterns : pattern_array :=
        (('0','0','1','0'),('0',('1','1'));
         
    begin 
        for i in patterns'range loop
            E <= patterns(i).E;
            A <= patterns(i).A;
            B <= patterns(i).B;
            
            wait for 1 ns;
            
            assert D0 = patterns(i).D0
              report "erro gate D0" severity error;
            assert D1 = patterns(i).D1
              report "erro gate D1" severity error;
            assert D2 = patterns(i).D2
              report "erro gate D2" severity error;
            assert D3 = patterns(i).D3
              report "erro gate D3" severity error;
        end loop;
        
        assert false report "END OF TEST" severity note;
        
        wait;
    end process;
end behave;```

解决方法

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