为什么我把它当作一个空的 opt-design？

问题描述

library IEEE;
use IEEE.std_logic_1164.all;

entity seg7ctrl is
 port
 (
 mclk : in std_logic;
 reset : in std_logic; 
 d0 : in std_logic_vector(3 downto 0);
 d1 : in std_logic_vector(3 downto 0);
 abcdefg : out std_logic_vector(6 downto 0);
 c : out std_logic
 );
end entity seg7ctrl;


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.seg7model_pkg.all;

architecture rtl1_c of seg7ctrl is
signal count: std_logic_vector(19 downto 0):= "00000000000000000000";
begin  
process (mclk,reset) is  
    begin
        if rising_edge(mclk) then
                count<= std_logic_vector(unsigned(count)+1);
        end if;
        c <= count(count'high);
        set_display_c(d0,abcdefg); 
        set_display_c(d1,abcdefg);
        if rising_edge(reset) then
            count<= "00000000000000000000";                 
        end if;     
end process;
end rtl1_c;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity self_test is
end self_test;

architecture self_test of self_test is 
component  seg7ctrl is
    port (
            mclk : in std_logic;
        reset : in std_logic;
        d0 : in std_logic_vector(3 downto 0);
        d1 : in std_logic_vector(3 downto 0);
        abcdefg : out std_logic_vector(6 downto 0);
        c : out std_logic);
end component seg7ctrl;

signal mclk          : std_logic := '0';
constant half_period : time := 5 ns;
signal  reset        : std_logic := '0';
signal  d0           : std_logic_vector(3 downto 0) := "0000";
signal  d1           : std_logic_vector(3 downto 0) := "0000";
signal  abcdefg      : std_logic_vector(6 downto 0) := "0000000";
signal  c            : std_logic := '0';
signal counter       : unsigned(3 downto 0) := "0000";
signal second_tick : std_logic := '0';

type rom_array_D1 is array (0 to 15) of std_logic_vector (3 downto 0);
constant rom_D1: rom_array_D1:= ( "0001","0011","0100","0000","0101","0111","1000","1001","1010","1100","0110","0000");

type rom_array_D0 is array (0 to 15) of std_logic_vector (3 downto 0);
constant rom_D0: rom_array_D0:= ( "0010","1011","0000");

begin
    UUT: entity work.seg7ctrl(rtl1_c)
        port map (
            mclk     => mclk,reset    => reset,d0       => d0,d1       => d1,abcdefg  => abcdefg,c        => c);

    mclk <= not mclk after half_period; 
    reset <= not reset after 18 sec;

    process (c) is
        variable count: integer range 0 to 100 := 0;
    begin
        if rising_edge(c) then
            d0<="ZZZZ";
            d1<=rom_D1(to_integer(unsigned(counter)));
        end if;
        if falling_edge(c) then
            d1<="ZZZZ";
            d0<=rom_D0(to_integer(unsigned(counter)));
    end if;
        if falling_edge(c) then
            count:=count+1;
        end if;
        if count=99 then 
            second_tick <= '1';
        elsif count=50 then
            second_tick <= '0';
            count:=0;
        end if;
    end process;
        
    process (second_tick,reset) is
    begin
        if rising_edge(reset) then
            counter   <= "0000";
        end if;
        if rising_edge(second_tick) then
            counter <= counter + 1;                                 
        end if;         
    end process;
end self_test;

第一部分是实体，第二部分是架构，第三部分是自测。它们位于单独的文件中，这就是库位于每个部分之上的原因。我在 vivado 中有架构和 self_test 作为设计源。我在综合设计时没有问题，但每次运行实现时都会出现此错误：

[Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design.  Check whether you 
have instantiated and connected all of the top level ports.

我在任何地方都找不到导致此错误的确切原因。因此，如果有人知道可能导致错误的原因，那就太好了

解决方法

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