问题描述
我正在做一项大学作业,代码是从旧板上给出的,我不得不在新板上运行它。 (Nexys --> Basys3)。在其中一项任务中,需要将七段计数为 9(0-1-2-3-4-5-6-7-8-9),然后再回到 0(9-8-7- 6-5-4-3-2-1-0)。我做了这个任务,但老师不喜欢它到底是如何计算的。它类似于 (0-1-2-3-4-5-6-7-8-9 -> 9-8-7-6-5-4-3-2-1-0-0-1. ..) 但应该是 (...1-0-1...).
还有一个任务是,对于每个新数字,小点应该改变它的值 (0 1) 老实说,我不完全理解 VHDL 语法。这使它变得更加困难。
所以我的问题是:
- 目前我不明白为什么我在计数时有这个额外的“0”......我该如何解决这个问题?
- 如何让小点改变它的值使其“闪烁”?
是的,我知道您应该简单地更改正确位的值,例如...seg(7) <= '1';
但出于某种原因,即使这也不起作用...或者我又不完全理解某些内容。
代码:
.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Nexysdemo is
Port (
clk : in std_logic;
btn : in std_logic_vector(3 downto 0);
sw : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0); -- Cathode patterns of 7-segment
an : out std_logic_vector(3 downto 0); --4 Anode signals
seg : out std_logic_vector(7 downto 0));
end Nexysdemo;
architecture Behavioral of Nexysdemo is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal clkdiv : std_logic_vector(24 downto 0); -- 24 downto 0
signal cntr : std_logic_vector(4 downto 0); -- 3 downto 0
signal cclk : std_logic;
signal dig : std_logic_vector(6 downto 0);
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
led <= sw;
dig <=
"0111111" when cntr = "00000" else --0
"0000110" when cntr = "00001" else --1
"1011011" when cntr = "00010" else --2
"1001111" when cntr = "00011" else --3
"1100110" when cntr = "00100" else --4
"1101101" when cntr = "00101" else --5
"1111101" when cntr = "00110" else --6
"0000111" when cntr = "00111" else --7
"1111111" when cntr = "01000" else --8
"1101111" when cntr = "01001" else --9
"1111111" when cntr = "01010" else --8
"0000111" when cntr = "01011" else --7
"1111101" when cntr = "01100" else --6
"1101101" when cntr = "01101" else --5
"1100110" when cntr = "01110" else --4
"1001111" when cntr = "01111" else --3
"1011011" when cntr = "10000" else --2 A
"0000110" when cntr = "10001" else --1 B
"0111111" when cntr = "10010" else --0 C
"0000000";
seg(6 downto 0) <= not dig;
an <= btn;
seg(7) <= '1';
-- Divide the master clock (100Mhz) down to a lower frequency.
process (clk)
begin
if clk = '1' and clk'Event then
clkdiv <= clkdiv + 1;
end if;
end process;
cclk <= clkdiv(24); --24
process (cclk)
begin
if cclk = '1' and cclk'Event then
if cntr = "10010" then --1001
cntr <= "00000";
else
cntr <= cntr + 1;
end if;
end if;
end process;
end Behavioral;
Basys-3-Master.xdc
# Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
##7 segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property PACKAGE_PIN V7 [get_ports {seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
##Buttons
set_property PACKAGE_PIN U18 [get_ports {btn[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}]
set_property PACKAGE_PIN T18 [get_ports {btn[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}]
set_property PACKAGE_PIN W19 [get_ports {btn[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}]
set_property PACKAGE_PIN T17 [get_ports {btn[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
## Configuration options,can be used for all designs
set_property CONfig_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
解决方法
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