在 8 位组件中测试 24 位信号

问题描述

我一直在做我的家庭作业，我们必须创建一个奇偶校验位发生器电路，对于 8 位序列输出一个 9 位序列，其中新的是奇偶校验位（如果有一个，它被设置为 1序列中为 1 的奇数位）。这是它的代码：

library ieee;
use ieee.std_logic_1164.all;

entity top is
      port( 
            idata:in bit_vector(7 downto 0);
            odata:out bit_vector(8 downto 0)
            );
end top;

architecture parity_gen of top is
signal temp : bit_vector(5 downto 0);

begin
    temp(0)<=idata(0) xor idata(1);
    temp(1)<=temp(0) xor idata(2);
    temp(2)<=temp(1) xor idata(3);
    temp(3)<=temp(2) xor idata(4);
    temp(4)<=temp(3) xor idata(5);
    temp(5)<=temp(4) xor idata(6);
    odata(0)<= temp(5) xor idata(7);
    odata(1)<=idata(0);
    odata(2)<=idata(1);
    odata(3)<=idata(2);
    odata(4)<=idata(3);
    odata(5)<=idata(4);
    odata(6)<=idata(5);
    odata(7)<=idata(6);
    odata(8)<=idata(7);
end parity_gen;

现在我还为它创建了一个测试平台程序，如下所示：

library ieee;
use ieee.std_logic_1164.all;

entity top_tb is end top_tb;

architecture behavior of top_tb is
    component top is
        port( 
            idata:in bit_vector(7 downto 0);
            odata:out bit_vector(8 downto 0)
            );
    end component;
    signal input  : bit_vector(7 downto 0);
    signal output : bit_vector(8 downto 0);
begin
    uut: top port map (
        idata(7 downto 0) => input(7 downto 0),odata(8 downto 0) => output(8 downto 0)
    );

    stim_proc: process
    begin
        input <= "10100101"; wait for 10 ns; assert output = "101001010" report "test Failed";
        report "Top testbench finished";
        wait;
    end process;
end;

有没有办法针对更长的输入序列测试这个组件，比如说 24 位，我必须在代码中进行哪些实际更改才能实现这一目标？

Input : [ 1 0 1 0 0 1 0 1     1 1 0 0 0 1 1 1    1 0 1 0 1 1 0 0  ]
Output: [ 1 0 1 0 0 1 0 1 0   1 1 0 0 0 1 1 1 1  1 0 1 0 1 1 0 0 0]

我基本上想做这样的事情：

input <= "101001011100011110101100"; wait for 10 ns; assert output = "101001010110001111101011000" report "test Failed";

解决方法

您可以创建一个 forloop 并在检查类似大小的输出数组的同时迭代输入数组的元素

type t_in_array is array 0 to num_of_inputs of std_logic_vector(7 downto 0);
  signal s_input_arr : t_in_array := ("10100101",...); 
type t_out_array is array 0 to num_of_inputs of std_logic_vector(8 downto 0);
  signal s_exp_out_arr: t_out_array := ("101001010",...);

stim_proc: process
begin
for i in 0 to num_of_inputs
  input <= s_input_arr(i);
  wait for 10 ns;
  assert output = s_exp_out_arr(i)
    report "failed";
end loop;
wait;
end process stim_proc;

在没有测试 FYI 的情况下即时编写。

ghdl vhdl