问题描述
背景
我对各种 bluespec 演示文稿和文档的理解是，如果两个规则都修改同一个寄存器，则它们不能在同一周期中运行。
例如，我读过“BSV By Example”（Amazon，other），
同样，某些硬件资源限制，例如事实 硬件线只能在每个时钟中用一个值驱动， 将阻止一些规则对在一个时钟中一起执行 因为他们都需要那个资源。我们称之为“规则资源 冲突”。
同样，Arvind @ MIT 似乎say 不允许“双写错误”。
然后
最近我正在阅读课程“8.6 RWires and atomicity”，遇到类似以下的代码：
package Tb;
import FIFO::*;
// ----------------------------------------------------------------
// A top-level module connecting the stimulus generator to the DUT
(* synthesize *)
module mkTb (Empty);
FIFO#(int) f <- mkPipelineFIFO; // Instantiate a FIFO (see module def below)
// ----------------
// Step 'state' from 1 to 10
Reg#(int) state <- mkReg (0);
rule step_state;
if (state > 9) $finish (0);
state <= state + 1;
endrule
// ----------------
// Enqueue and dequeue something on every cycle (in every state)
rule e;
let x = state * 10;
f.enq (x);
$display ("State %0d: Enqueue %0d",state,x);
endrule
rule d;
let y = f.first ();
f.deq ();
$display ("State %0d: Dequeue %0d",y);
endrule
// ----------------
// Also clear the FIFO in state 2
rule clear_counter (state == 2);
f.clear ();
$display ("State %0d: Clearing",state);
endrule
endmodule: mkTb
// ----------------------------------------------------------------
// A 1-element "pipeline" FIFO
(* synthesize *)
module mkPipelineFIFO (FIFO#(int));
// STATE ----------------
// The FIFO
Reg#(Bool) full <- mkReg (False);
Reg#(int) data <- mkRegU;
RWire#(int) rw_enq <- mkRWire; // enq method signal
pulseWire pw_deq <- mkpulseWire; // deq method signal
Bool enq_ok = ((! full) || pw_deq);
Bool deq_ok = full;
// RULES ----------------
// This rule does all the work,taking into account that 'enq()' and
// 'deq()' may be called simultaneously when the FIFO is already full
rule rule_update_final (isValid(rw_enq.wget) || pw_deq);
full <= isValid(rw_enq.wget);
data <= fromMaybe (?,rw_enq.wget);
$display("rule_update_final");
endrule
// INTERFACE ----------------
method Action enq(v) if (enq_ok);
rw_enq.wset(v);
endmethod
method Action deq() if (deq_ok);
pw_deq.send ();
endmethod
method first() if (full);
return data;
endmethod
method Action clear();
full <= False;
endmethod
endmodule: mkPipelineFIFO
endpackage: Tb
运行此代码导致：
State 0: Enqueue 0
rule_update_final
State 1: Dequeue 0
State 1: Enqueue 10
rule_update_final
State 2: Dequeue 10
State 2: Enqueue 20
State 2: Clearing
rule_update_final
State 3: Dequeue 20
State 3: Enqueue 30
rule_update_final
State 4: Dequeue 30
State 4: Enqueue 40
rule_update_final
State 5: Dequeue 40
State 5: Enqueue 50
rule_update_final
State 6: Dequeue 50
State 6: Enqueue 60
rule_update_final
State 7: Dequeue 60
State 7: Enqueue 70
rule_update_final
State 8: Dequeue 70
State 8: Enqueue 80
rule_update_final
State 9: Dequeue 80
State 9: Enqueue 90
rule_update_final
State 10: Dequeue 90
State 10: Enqueue 100
我相信以下警告（不是错误！）消息似乎是相关的：
Warning: "Tb.bsv",line 38,column 10: (G0117)
Rule `rule_update_final' shadows the effects of `clear' when they execute in
the same clock cycle. Affected method calls:
full.write
To silence this warning,use the `-no-warn-action-shadowing' flag.
问题
修改同一个 rule_update_final 寄存器的两个规则（clear_counter 和 full）怎么可能在同一个周期内运行？
解决方法
暂无找到可以解决该程序问题的有效方法，小编努力寻找整理中！
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