问题描述
我知道，如何使用 yosys 从 verilog .dot 文件编译 .v 文件，以便以图形方式检查 verilog 设计。我在我的 makefile 中使用了这样的目标：
dot:
yosys \
-p "read_verilog -sv -formal $(file_main).v" \
-p "hierarchy -check -top $(module_top)" \
-p "proc" \
-p "show -prefix $(file_main) -notitle -colors 2 -width -format dot"
xdot $(file_main).dot
但是有一个问题。编译 .dot 文件并用 `xdot 打开后，一切看起来更像是软件流程图，但我希望它看起来更像是电子原理图。目前有没有办法实现这一目标？
我知道 yosis 也可以从 verilog .blif 文件中创建 .v 文件。我通常在我的 makefile 中这样做：
yosys \
-p "synth_ice40 -top $(module_top) -blif $(file_main).blif" \
$(file_main).v
带有 .blif 扩展名的文件实际上是一个 netlist 文件 (source)！那么是否有任何程序可以以某种方式预览它们？或者也许是一个可以解析它们的解析器，这样我就可以以某种方式预览它们的原理图？
NETLISTSVG
有人建议使用工具 netlistsvg，但该工具并未积极开发，而且有一个令人讨厌的缺点。它不接受类型 inout。所以如果我使用这个 makefile 目标：
svg:
yosys \
-p "read_verilog -sv -formal $(file_main).v" \
-p "hierarchy -check -top $(module_top)" \
-p "proc" \
-p "write_json $(file_main).json"
netlistsvg -o $(file_main).svg $(file_main).json
"d": {
"direction": "input","bits": [ 2 ]
},"c": {
"direction": "input","bits": [ 3 ]
},"r": {
"direction": "input","bits": [ 4 ]
},"q": {
"direction": "inout","bits": [ 5 ]
}
},"cells": {
"$and$d_flip_flop_rizing_clr.v:25$1": {
"hide_name": 1,"type": "$and","parameters": {
"A_SIGNED": "00000000000000000000000000000000","A_WIDTH": "00000000000000000000000000000001","B_SIGNED": "00000000000000000000000000000000","B_WIDTH": "00000000000000000000000000000001","Y_WIDTH": "00000000000000000000000000000001"
},"attributes": {
"src": "d_flip_flop_rizing_clr.v:25.17-25.22"
},"port_directions": {
"A": "input","B": "input","Y": "output"
},"connections": {
"A": [ 6 ],"B": [ 7 ],"Y": [ 8 ]
}
},"$and$d_flip_flop_rizing_clr.v:26$2": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:26.17-26.22"
},"connections": {
"A": [ 9 ],"B": [ 6 ],"Y": [ 10 ]
}
},"$and$d_flip_flop_rizing_clr.v:28$4": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:28.17-28.25"
},"connections": {
"A": [ 11 ],"B": [ 9 ],"Y": [ 12 ]
}
},"$and$d_flip_flop_rizing_clr.v:30$6": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:30.17-30.22"
},"connections": {
"A": [ 13 ],"B": [ 14 ],"Y": [ 15 ]
}
},"$and$d_flip_flop_rizing_clr.v:31$7": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:31.17-31.25"
},"connections": {
"A": [ 15 ],"B": [ 2 ],"Y": [ 16 ]
}
},"$and$d_flip_flop_rizing_clr.v:34$10": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:34.17-34.22"
},"Y": [ 17 ]
}
},"$and$d_flip_flop_rizing_clr.v:35$11": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:35.17-35.25"
},"connections": {
"A": [ 17 ],"B": [ 5 ],"Y": [ 18 ]
}
},"$and$d_flip_flop_rizing_clr.v:37$13": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:37.17-37.22"
},"connections": {
"A": [ 19 ],"Y": [ 20 ]
}
},"$and$d_flip_flop_rizing_clr.v:38$14": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:38.17-38.25"
},"connections": {
"A": [ 20 ],"B": [ 3 ],"Y": [ 21 ]
}
},"$and$d_flip_flop_rizing_clr.v:41$17": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:41.17-41.22"
},"Y": [ 11 ]
}
},"$not$d_flip_flop_rizing_clr.v:27$3": {
"hide_name": 1,"type": "$not","attributes": {
"src": "d_flip_flop_rizing_clr.v:27.17-27.23"
},"connections": {
"A": [ 8 ],"Y": [ 5 ]
}
},"$not$d_flip_flop_rizing_clr.v:29$5": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:29.14-29.20"
},"connections": {
"A": [ 12 ],"Y": [ 13 ]
}
},"$not$d_flip_flop_rizing_clr.v:32$8": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:32.14-32.20"
},"connections": {
"A": [ 16 ],"Y": [ 9 ]
}
},"$not$d_flip_flop_rizing_clr.v:33$9": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:33.14-33.17"
},"connections": {
"A": [ 4 ],"Y": [ 14 ]
}
},"$not$d_flip_flop_rizing_clr.v:36$12": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:36.14-36.20"
},"connections": {
"A": [ 18 ],"Y": [ 7 ]
}
},"$not$d_flip_flop_rizing_clr.v:39$15": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:39.14-39.20"
},"connections": {
"A": [ 21 ],"Y": [ 6 ]
}
},"$not$d_flip_flop_rizing_clr.v:40$16": {
"hide_name": 1,"attributes": {
"src": "d_flip_flop_rizing_clr.v:40.14-40.20"
},"connections": {
"A": [ 10 ],"Y": [ 19 ]
}
}
},"netnames": {
"$and$d_flip_flop_rizing_clr.v:25$1_Y": {
"hide_name": 1,"bits": [ 8 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:25.17-25.22"
}
},"$and$d_flip_flop_rizing_clr.v:26$2_Y": {
"hide_name": 1,"bits": [ 10 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:26.17-26.22"
}
},"$and$d_flip_flop_rizing_clr.v:28$4_Y": {
"hide_name": 1,"bits": [ 12 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:28.17-28.25"
}
},"$and$d_flip_flop_rizing_clr.v:30$6_Y": {
"hide_name": 1,"bits": [ 15 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:30.17-30.22"
}
},"$and$d_flip_flop_rizing_clr.v:31$7_Y": {
"hide_name": 1,"bits": [ 16 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:31.17-31.25"
}
},"$and$d_flip_flop_rizing_clr.v:34$10_Y": {
"hide_name": 1,"bits": [ 17 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:34.17-34.22"
}
},"$and$d_flip_flop_rizing_clr.v:35$11_Y": {
"hide_name": 1,"bits": [ 18 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:35.17-35.25"
}
},"$and$d_flip_flop_rizing_clr.v:37$13_Y": {
"hide_name": 1,"bits": [ 20 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:37.17-37.22"
}
},"$and$d_flip_flop_rizing_clr.v:38$14_Y": {
"hide_name": 1,"bits": [ 21 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:38.17-38.25"
}
},"$and$d_flip_flop_rizing_clr.v:41$17_Y": {
"hide_name": 1,"bits": [ 11 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:41.17-41.22"
}
},"$not$d_flip_flop_rizing_clr.v:27$3_Y": {
"hide_name": 1,"bits": [ 5 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:27.17-27.23"
}
},"$not$d_flip_flop_rizing_clr.v:29$5_Y": {
"hide_name": 1,"bits": [ 13 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:29.14-29.20"
}
},"$not$d_flip_flop_rizing_clr.v:32$8_Y": {
"hide_name": 1,"bits": [ 9 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:32.14-32.20"
}
},"$not$d_flip_flop_rizing_clr.v:33$9_Y": {
"hide_name": 1,"bits": [ 14 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:33.14-33.17"
}
},"$not$d_flip_flop_rizing_clr.v:36$12_Y": {
"hide_name": 1,"bits": [ 7 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:36.14-36.20"
}
},"$not$d_flip_flop_rizing_clr.v:39$15_Y": {
"hide_name": 1,"bits": [ 6 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:39.14-39.20"
}
},"$not$d_flip_flop_rizing_clr.v:40$16_Y": {
"hide_name": 1,"bits": [ 19 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:40.14-40.20"
}
},"_00_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:4.8-4.12"
}
},"_01_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:5.8-5.12"
}
},"_02_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:6.8-6.12"
}
},"_03_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:7.8-7.12"
}
},"_04_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:8.8-8.12"
}
},"_05_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:9.8-9.12"
}
},"_06_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:10.8-10.12"
}
},"_07_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:11.8-11.12"
}
},"_08_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:12.8-12.12"
}
},"_09_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:13.8-13.12"
}
},"_10_": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:14.8-14.12"
}
},"c": {
"hide_name": 0,"bits": [ 3 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:15.9-15.10"
}
},"d": {
"hide_name": 0,"bits": [ 2 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:16.9-16.10"
}
},"e": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:17.8-17.9"
}
},"f": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:18.8-18.9"
}
},"g": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:19.8-19.9"
}
},"h": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:20.8-20.9"
}
},"i": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:21.8-21.9"
}
},"j": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:22.8-22.9"
}
},"q": {
"hide_name": 0,"attributes": {
"src": "d_flip_flop_rizing_clr.v:23.9-23.10"
}
},"r": {
"hide_name": 0,"bits": [ 4 ],"attributes": {
"src": "d_flip_flop_rizing_clr.v:24.9-24.10"
}
}
}
}
}
}
但是 netlistsvg 命令失败并出现错误：
netlistsvg -o d_flip_flop_rizing_clr.svg d_flip_flop_rizing_clr.json
/usr/local/lib/node_modules/netlistsvg/bin/netlistsvg.js:55
throw Error(JSON.stringify(ajv.errors,null,2));
^
Error: [
{
"keyword": "enum","dataPath": "/modules/d_flip_flop_rizing_clr/ports/q/direction","schemaPath": "#/properties/modules/additionalProperties/properties/ports/additionalProperties/properties/direction/enum","params": {
"allowedValues": [
"input","output"
]
},"message": "should be equal to one of the allowed values"
}
]
at /usr/local/lib/node_modules/netlistsvg/bin/netlistsvg.js:55:19
at /usr/local/lib/node_modules/netlistsvg/bin/netlistsvg.js:41:17
at FSReqCallback.readFileAfterClose [as oncomplete] (internal/fs/read_file_context.js:63:3)
make: *** [makefile:152: svg] Error 1
它正在抱怨 inout 类型。很不完整...
解决方法
您可能想看看NetlistSVG。它可以从 Yosys 创建的 JSON 网表中绘制原理图。