vhdl 32 位加法和减法，带溢出检测有符号数

问题描述

Hw：我正在研究带有溢出检测的 32 位加法和减法。它基于 4 位加法器组件，后者基于全加器组件。当减为 1 --> 做减法，否则加法以下是我到目前为止所拥有的，只有 sum 和 overflow 有问题。我不知道为什么总和不正确（例如：20-12=8）。请帮忙解决这个问题！对于溢出，我试过 overflow <= '1' when a(31)='1' and var(31)='1' and s(31)='0' else '1' when a(31)='0' and var(31)='0' and s(31)/='0' else '0'; 但它不起作用并给我同样的溢出。 32 位加法器/子：

use  ieee.std_logic_1164.all;

entity thirty_two_bit_adder is
     port (a,b: in std_logic_vector(31 downto 0);
        subtract: in std_logic;
        sum: out std_logic_vector (31 downto 0);
        overflow: out std_logic);
end thirty_two_bit_adder;

architecture fa_arch of thirty_two_bit_adder is
     component four_bit_adder
    port (a,b: in std_logic_vector(3 downto 0);
           cin : in std_logic;
           sum: out std_logic_vector (3 downto 0);
           cout: out std_logic);
     end component;
signal t: std_logic_vector (6 downto 0);
signal var: std_logic_vector (31 downto 0); 
signal s: std_logic_vector(31 downto 0);
begin
--LHS: 4-bit compnent ports => RHS: 32-bit entity ports
    var(31 downto 0)<= not b(31 downto 0) when subtract='1' else b(31 downto 0);
    FA0: four_bit_adder port map (a(3 downto 0) => a(3 downto 0),b(3 downto 0) => var(3 downto 0),cin => subtract,sum(3 downto 0) => s(3 downto 0),cout => t(0));
    FA1: four_bit_adder port map (a(3 downto 0) => a(7 downto 4),b(3 downto 0) => var(7 downto 4),cin => t(0),sum(3 downto 0) => s(7 downto 4),cout => t(1));
    FA2: four_bit_adder port map (a(3 downto 0) => a(11 downto 8),b(3 downto 0) => var(11 downto 8),cin => t(1),sum(3 downto 0) => s(11 downto 8),cout => t(2));
    FA3: four_bit_adder port map (a(3 downto 0) => a(15 downto 12),b(3 downto 0) => var(15 downto 12),cin => t(2),sum(3 downto 0) => s(15 downto 12),cout => t(3));
    FA4: four_bit_adder port map (a(3 downto 0) => a(19 downto 16),b(3 downto 0) => var(19 downto 16),cin => t(3),sum(3 downto 0) => s(19 downto 16),cout => t(4));
    FA5: four_bit_adder port map (a(3 downto 0) => a(23 downto 20),b(3 downto 0) => var(23 downto 20),cin => t(4),sum(3 downto 0) => s(23 downto 20),cout => t(5));
    FA6: four_bit_adder port map (a(3 downto 0) => a(27 downto 24),b(3 downto 0) => var(27 downto 24),cin => t(5),sum(3 downto 0) => s(27 downto 24),cout => t(6));
    FA7: four_bit_adder port map (a(3 downto 0) => a(31 downto 28),b(3 downto 0) => var(31 downto 28),cin => t(6),sum(3 downto 0) => s(31 downto 28),cout => overflow);
    overflow <= '1' when a(31)/=a(30) and b(31)/=b(30) else
            '0';
end fa_arch;

测试用例：

-- -3 + -6 = -9 (0xFFFFFFF7) ***correct sum,but mine is overflow***
    subtract <= '0';
    a <= "11111111111111111111111111111101";
    b <= "11111111111111111111111111111010";

-- 20 - 12 = 8 (0x00000008)  ***I got 00000021 for sum***
    subtract <= '1';
    a <= "00000000000000000000000000010100";
    b <= "00000000000000000000000000001100";

-- Large positive - large negative = overflow ***mine is not overflow***
    subtract <= '1';
    
-- large positive + large positive = overflow ***mine is not overflow***
    subtract <= '0';
    
-- large negative - large negative = no overflow ***mine is overflow***
    subtract <= '1';

提前致谢！！

解决方法

您已经获得了驱动信号“溢出”的 FA7 组件。您还从内联代码驱动信号“溢出”。你通常不能两者都做，你会得到 X。

如果您的 4 位加法器组件构造正确，则 FA7 输出应该可以工作。

addition subtraction vhdl